All traditional clock multipliers exhibit some residual phase modulation of a multiplied clock at the frequency of a reference clock signal. The process of clock recovery in a receiver or a transmitter will cause a phase error appearing on the multiplied clock to be sampled at a frequency that is equal to a timing reference signal. This sampled phase error appears directly on the phase of the timing reference signal. The magnitude of this phase error is a function of a phase difference between the timing reference signal and the reference clock signal at the sampling instant. The shape of the function is a characteristic intrinsic to the clock multiplier.
A transmitter clock recovery loop operates based upon phase differences between timing reference signals so any phase error between the timing reference signals that is within a pass band of a transmitter phase detector filter will appear as a phase offset in the transmitter clock recovery loop. The resulting phase offset from phase modulation of the timing reference signals will depend on relative amplitudes and phases of the modulation sources (e.g., the sampling of the phase error on the multiplied clock by timing reference generators). System variables such as the propagation delay of a receiver timing reference signal from a receiver to a transmitter, along with a reset behavior of timing reference clock dividers, would in practice affect the phase error appearing between the timing reference signals at the input to the transmitter phase detector filter.
For example, referring to FIG. 1, there is shown an exemplary traditional pleisiochronous repeater system 100 comprising a receiver 102 and a transmitter 104. The receiver 102 comprises a clock multiplier 110, a clock recovery circuit 112, a sampler 114, a deserializer 116, a divide by K circuit 118, and a divide by 2 circuit 120. The clock recovery circuit 112 comprises an interpolator 122, a phase detector 124, and a filter 126. The transmitter 104 comprises a clock multiplier 130, a clock recovery circuit 132, a driver 134, a serializer 136, a divide by K circuit 138, and a divide by 2 circuit 140. The clock recovery circuit 132 comprises an interpolator 142, a phase detector 144, and a filter 146.
The receiver 102 receives a reference clock signal (refclk), which is multiplied by the clock multiplier 110 to generate a receiver multiplied clock signal (rmclk). The receiver multiplied clock signal (rmclk) is phase adjusted by the interpolator 122 based upon a receiver low frequency phase difference signal (rphase) to generate a receiver data clock signal (rdclk).
The receiver 102 also receives serial data, which is sampled by the sampler 114 using the receiver data clock signal (rdclk). The sampled serial data is deserialized by the deserializer 116 using the receiver data clock signal (rdclk), and a receiver word clock signal (rwclk) generated by the divide by K circuit 118. The deserializer 116 outputs a K-bit parallel data word. The receiver word clock signal (rwclk) is divided by the divide by 2 circuit 120, which outputs a receiver timing reference signal (rtref).
The serial data is also compared against the receiver data clock signal (rdclk) in the phase detector 124 in the clock recovery circuit 112 to determine if there is any phase difference therebetween. Any resulting high frequency phase difference components detected by the phase detector 124 are filtered out by the filter 126 in the clock recovery circuit 112, while any resulting low frequency phase difference components detected by the phase detector 124 are passed by the filter 126 in the clock recovery circuit 112. The filter 126 thus provides the receiver low frequency phase difference signal (rphase) to the interpolator 122.
The transmitter 104 receives the reference clock signal (refclk), which is multiplied by the clock multiplier 130 to generate a transmitter multiplied clock signal (tmclk). The transmitter multiplied clock signal (tmclk) is phase adjusted by the interpolator 142 based upon a transmitter low frequency phase difference signal (tphase) to generate a transmitter data clock signal (tdclk).
The transmitter 104 also receives a K-bit parallel data word either directly from the receiver 102 or from some intermediate circuitry (not shown). The received K-bit parallel data word is serialized by the serializer 136 using the transmitter data clock signal (tdclk), and a transmitter word clock signal (twclk) generated by the divide by K circuit 138. The serializer 136 outputs serial data to the driver 134, which outputs clocked serial data using the transmitter data clock signal (tdclk). The transmitter word clock signal (twclk) is divided by the divide by 2 circuit 140, which outputs a transmitter timing reference signal (ttref).
The transmitter 104 further receives the receiver timing reference signal (rtref) either directly from the receiver 102 or from some intermediate circuitry (not shown). The received receiver timing reference signal (rtref) is compared against the transmitter timing reference signal (ttref) in the phase detector 144 in the clock recovery circuit 132 to determine if there is any phase difference therebetween. Any resulting high frequency phase difference components detected by the phase detector 144 are filtered out by the filter 146 in the clock recovery circuit 132, while any resulting low frequency phase difference components detected by the phase detector 144 are passed by the filter 146 in the clock recovery circuit 132. The filter 146 thus provides the transmitter low frequency phase difference signal (tphase) to the interpolator 142.
In the traditional pleisiochronous repeater system 100, alignment of the transmitter word clock signal (twclk) with the K-bit parallel data word that is received at the transmitter 104 is attempted by forwarding phase information from the receiver 102 to the transmitter 104 using the receiver timing reference signal (rtref) which transitions at the same rate as the received K-bit parallel data word. However, when the frequency of the reference clock signal (refclk) is integer divisible by the frequency of the receiver timing reference signal (rtref) (e.g., one half the frequency of the received K-bit parallel data word), the receiver timing reference signal (rtref) is phase modulated at a frequency that is equal to an offset frequency of the serial data that is received at the receiver 102, with a modulation amplitude that is equal to the amplitude of phase modulation appearing on the receiver data clock signal (rdclk) at the frequency of the reference clock signal (refclk). For example, when the clock multiplier 110 has a multiplier value M that is equal to the product of the divider values for the divide by K circuit 118 and the divide by 2 circuit 120 (i.e., 2*K), the frequency of the receiver timing reference signal (rtref) is offset from the frequency of the reference clock signal (refclk) by an amount that is equal to the frequency of the reference clock signal (refclk) multiplied by a frequency difference between the frequency of the serial data that is received at the receiver 102 and the frequency of the receiver data clock (rdclk), divided by the frequency of the receiver data clock (rdclk) (e.g., if the frequency of the serial data is 2.5 GHz, and the frequency of the reference clock signal (refclk) is 156.25 MHz, then the frequency of the receiver timing reference signal (rtref) would be 156.28125 MHz). As mentioned above, in all traditional clock multipliers, phase modulation appearing on a multiplied clock is sampled at a frequency that is equal to a receiver timing reference signal, and appears on the receiver timing reference signal as a phase error. Thus, in this case, the phase error appearing on the receiver timing reference signal (rtref) traces out the phase modulation appearing on the receiver multiplied clock signal (rmclk) at a rate equal to the frequency offset between the receiver timing reference signal (rtref) and the reference clock signal (refclk). That is, the receiver interpolator 122 essentially traces out the phase error appearing on the receiver data clock signal (rdclk) as it rotates the phase of the receiver data clock signal (rdclk) to track the offset frequency of received serial data. The resulting phase modulation in the receiver timing reference signal (rtref) is extremely low frequency (e.g., 200 ppm of the received serial data rate), and passes through the filter 146 in the clock recovery circuit 132 in the transmitter 104. Phase modulation also occurs on the transmitter data clock signal (tdclk) and the transmitter word clock signal (twclk) when the transmitter clock recovery circuit 132 attempts to align the transmitter timing reference signal (ttref) to the receiver timing reference signal (rtref).
The phase modulation associated with the receiver timing reference signal (rtref) is detrimentally summed with the phase modulation associated with the transmitter data clock signal (tdclk) and the transmitter word clock signal (twclk) in the transmitter clock recovery circuit 132. A resulting modulation amplitude of the transmitter data clock signal (tdclk) and the transmitter word clock signal (twclk) will vary, depending on the relative phase relationship of the receiver timing reference signal (rtref) and the reference clock signal (refclk). This result is undesirable and often even unacceptable in many pleisiochronous repeater systems.
In view of the foregoing, it would be desirable to provide a pleisiochronous repeater system which minimizes or avoids the above-described inadequacies and shortcomings associated with traditional pleisiochronous repeater systems.